ESD protection has been a main concern in the reliability of integrated circuit (IC) products in submicron complimentary metal-oxide-silicon (CMOS) technologies. For example, gates in N-type metal metal-oxide-silicon (NMOS) and P-type metal-oxide-silicon (PMOS) transistors in input buffers of a CMOS IC are often directly connected to input pads of the IC, causing the CMOS input buffers to be vulnerable to ESD damage.
Grounded gate NMOS (GGNMOS) transistors and gate coupled NMOS (GCNMOS) transistors are a frequent choice for an ESD protection circuit in such technologies. Such a device operates to provide ESD protection by triggering a parasitic lateral bipolar transistor inherent in the MOS structure where the source and drain regions of the MOS transistor constitute the emitter and collector of the lateral bipolar transistor and the substrate constitutes the base. See, for example, A. Amerasekera and C. Durvery, ESD in Silicon Integrated Circuits, pp. 81-95, 137-148 (2d Ed., Wiley, 2002), which is incorporated herein by reference.
A conventional GGNMOS transistor 110 and I/O pad 180 are shown in FIG. 1. Transistor 110 comprises a source 120, a drain 130 and a gate 140. The source and drain are regions of N-type conductivity formed in a substrate or well of P-type conductivity. The substrate or well, which is sometimes referred to as the body, is represented schematically in FIG. 1 by element 150. As shown in FIG. 1, gate 140, source 120 and body 150 are all connected to ground. Drain 130 is connected to I/O pad 180. As will be appreciated by those skilled in the art, a typical integrated circuit has numerous such I/O pads protected by GGNMOS ESD circuits.
P-type body 150 and N-type source region 120 form a first P-N junction and P-type body 150 and N-type drain region 130 form a second P-N junction. As a result, a parasitic lateral bipolar transistor is present in transistor 110 having a base-emitter junction that is the first P-N junction and a base-collector junction that is the second P-N junction. In FIG. 1 the second P-N junction is schematically represented by diode 160. In the event of a positive voltage ESD event on the input pad, the second P-N junction is driven into breakdown and avalanche and the parasitic transistor is triggered into conduction to discharge the ESD pulse.
The circuit of FIG. 1 is susceptible to poor performance due to leakage currents if I/O pad 180 experiences negative voltages during regular operations that are sufficient to turn on diode 160. For example, negative voltages may be present on test pads used to monitor the output of voltage regulators. To prevent such leakage currents, it is conventional to insert a diode 170 in series between the GGNMOS transistor 110 and the I/O pad 180 as shown in FIG. 2. In this arrangement, even if diode 160 becomes forward biased, diode 170 is reverse biased and there is no leakage path. Diode 170 has the disadvantage that during ESD operation it increases the voltage at the I/O pad by an amount equal to Vg+RD IESD where Vg is the voltage drop across diode 160, RD is the resistance of diode 160 and IESD is the electrostatic discharge current through diode 160.
Diode 170 also eliminates the discharge path through GGNMOS transistor 110 for any negative electrostatic discharge. This is a major disadvantage since positive and negative electrostatic discharges are possible on every I/O pad. One solution is to connect a series of diodes between the I/O pad and ground with the cathode connected to the I/O pad and the anode to ground. This, however, is not an attractive alternative because it takes up too much area on the semiconductor substrate.